The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having an output circuit for providing a plurality of signals from an internal circuit to output pads in parallel.
In recent years, as the number of output pins in a large-scale LSI has increased, a plurality of output buffer circuits are used to provide an output signal from an internal circuit to an output pin via an output pad. Each buffer circuit has a relatively large transistor for rapidly driving large capacitance loads, such as an external semiconductor chip and wirings on a packaging substrate. When the buffer circuits operate simultaneously, the simultaneous switching operation of the transistors in the output buffer circuits tends to generate power supply noise. Therefore, it is required that such power supply noise be suppressed.
FIG. 1 is a schematic block diagram showing an output circuit 100 mounted on a conventional semiconductor device. Each of a plurality of flip-flop circuits 1a and 1b receives data da1-dan and db1-dbn from internal circuits, and provides the data da1-dan and db1-dbn to a corresponding one of buffer circuits 2, in response to the rise of a corresponding clock signal CLKA or CLKB. The buffer circuits 2 amplify the data da1-dan and db1-dbn and provide output signals DA1 to DAn and DB1 to DBn to corresponding output pads 3.
The clock signal CLKA is generated by frequency-dividing a reference clock signal CLKS generated by a PLL circuit 4 with a frequency dividing circuit 5a. The clock signal CLKb is generated by frequency-dividing the clock signal CLKA from the frequency dividing circuit 5a into two with a frequency dividing circuit 5b. Accordingly, the flip-flop circuits 1a and the flip-flop circuits 1b operate on different clock signals.
In the output circuit 100, as shown in FIG. 2, a potential of a low potential power supply Vss temporarily rises to generate noise N when H level output signals DA1 to DAn and DB1 to DBn, which are being output from the buffer circuits 2, drop to L levels synchronously in response to the rise of the clock signals CLKA and CLKB. This noise N is referred to as “simultaneous switching output (SSO)” noise. If the SSO noise exceeds a tolerable value, it may cause erroneous functioning of other circuits commonly using the low potential power supply Vss.
Japanese Patent Laid-Open Publication No. 09-93108 discloses a technique for suppressing SSO noise by shifting the phases of clock signals provided to a plurality of output buffer circuits.